This paper deals with the problems involved in testing large mixed-signal ICs. To assist in generating test patterns of large mixed-signal circuits for functional tests, a fault model "voltage stuck-at fault" and a fast fault simulation algorithm are proposed. In this voltage stuck-at fault model, a signal line sticks to a constant voltage level. Under the assumption that the blocks in a circuit are identically designed as current-independent, i.e. their input impedance is regarded as infinite and their output impedance as zero. To verify the validity of this fault model, fault analysis was applied to several bipolar ICs. The analysis of open and short faults between terminals of transistors and resistors shows that this fault model has sufficient coverage (more than 50% of the faults) to test mixed-signal circuits. Based on this fault model, a fault simulation algorithm has been designed. The fault simulation is realized by an event driven method and a concurrent method and detects voltage stuck-at faults. These methods are essential for digital fault simulation and are extremely effective to high speed simulation. Actually, a fault simulator was implemented, and some test circuits were simulated. The simulator was found to be more than 50 times faster than the conventional one which was based on the circuit simulation.
�@